1. Field of the Invention
The present invention relates to a power amplifier of the type including a bootstrap capacitor. More particularly, the present invention relates to a circuit for clamping the bootstrap voltage of the bootstrap capacitor in an output stage of the power amplifier so that this voltage does not reach or exceed the breakdown voltage of transistors of the output stage.
2. Discussion of the Related Art
FIG. 1A partially shows a bootstrapped output stage of a conventional amplifier including a bootstrap capacitor. A bootstrap capacitor is frequently used in audio amplifiers to force full conduction of the high-side transistor of the output stage of the amplifier in order to deliver maximum power to the load with lower energy dissipation in the amplifier. Amplifier 1 has a positive supply terminal 2 and a negative supply terminal 3 which are respectively connected to a positive supply line +Vcc and to a negative supply line -Vcc (or ground). The output stage includes a high-side transistor M1 and a low-side transistor M2, for example N-channel MOS transistors, connected in series between terminals 2 and 3. The gate of transistor M1 is coupled to a bootstrap terminal 5 through a current source 4. The source of transistor M1, connected to the drain of transistor M2, constitutes the output terminal 6 of the amplifier 1.
The gate of transistor M1 is connected to supply line -Vcc through a series connection of two N-channel MOS transistors M3 and M4. Transistor M3 is diode-connected and transistor M4 is controlled by the drive voltage Vin provided to the output stage. The gate of transistor M2 is connected to the output of an operational amplifier 7. The inverting input of amplifier 7 is connected to terminal 6, and the non-inverting input is connected to the node N between transistors M3 and M4. With this construction, amplifier 7 drives transistor M2 such that the voltage at terminal 6 equals the voltage at node N. Transistors M1 and M3 act as a current mirror, wherein transistor M1 replicates the current of source 4 with an amplification factor depending on the W/L ratios of transistors M1 and M3.
An external bootstrap capacitor C having a high capacitance value is connected between terminals 5 and 6. This bootstrap capacitor C serves to provide the high-side transistor Ml with enough gate voltage Vg, so that the output voltage may reach the supply voltage +Vcc in any load conditions. Terminal 5 is coupled to line +Vcc through a diode D1 and an NPN transistor Q1. The base of transistor Q1 is coupled to line +Vcc through a current source 8 and to terminal 6 through a Zener diode DZ1.
FIG. 1B illustrates the operation of the bootstrapped output stage of FIG. 1A. The output voltage, at terminal 6, is shown at maximum swing, i.e., it varies between the two supply voltages -Vcc and +Vcc. When the output voltage 6 reaches its lowest value -Vcc (transistor M1 is off and transistor M2 is on), capacitor C charges substantially up to the Zener voltage Vz1 of diode DZ1 through diode D1 and transistors Q1 and M2. Zener voltage Vz1, which substantially corresponds to the maximum gatesource voltage of transistor M1, is chosen such that transistor M1 is suitably driven in full load conditions.
When the output voltage 6 reaches its highest value +Vcc (transistor M1 is on and transistor M2 is off), the bootstrap voltage 5 is equal to the output voltage (+Vcc), plus the voltage across capacitor C. Since capacitor C has a high value of capacitance and hardly discharges, the bootstrap voltage 5 reaches a value substantially equal to +Vcc +Vz1.
As shown by hatched areas, the gate voltage Vg of transistor M1 varies between the output voltage 6 and the bootstrap voltage 5, depending on the load conditions. For example, in full load conditions, the gate voltage Vg may be 10 volts higher than the output voltage, while, in no-load conditions, the gate voltage Vg may only be 2 volts higher. In this example, the Zener voltage Vz1 would be chosen above 10 volts.
A problem of such an output stage arises in applications where the supply voltage is not regulated. The supply voltage may then unpredictably reach a value close to the breakdown voltage of the components of the amplifier. Although the supply voltage is then still at an acceptable value, the gate voltage Vg of transistor M1 will exceed the supply voltage and cause the destruction of components, for example of transistor M4. Therefore, a large security margin must be taken for the supply voltage, resulting in a power loss of the amplifier.
FIG. 2 shows a conventional solution for reducing the supply voltage security margin. All the elements of FIG. 1A, except for capacitor C, are integrated on the same chip 1. An external circuit 9 is used to limit the voltage applied to bootstrap terminal 5. Capacitor C is no longer connected to bootstrap terminal 5 as in FIG. 1A. Instead, it is connected to supply line +Vcc through a diode D2. The voltage at terminal 5 is set by the emitter of a bipolar transistor T whose collector is connected to a node A between capacitor C and diode D2. The base of transistor T is coupled to ground or to line -Vcc through a Zener diode DZ2 and to the collector of transistor T through a bias resistor R.
With this construction, when the voltage at node A exceeds the Zener voltage Vz2 of diode DZ2, transistor T limits the voltage at terminal 5 to the Zener voltage Vz2. The gate voltage Vg of transistor M1 will therefore always be below Zener voltage Vz2. Zener voltage Vz2 is preferably chosen close to the circuit's breakdown voltage in order to obtain maximum power from the amplifier.
However, the Zener voltage Vz2 varies with variations of process and temperature. This makes it difficult to accurately control the maximum bootstrap voltage, whereby a security margin is still necessary for the supply voltage. This security margin is however smaller than that needed in the circuit of FIG. 1A.
Another drawback of the circuit of FIG. 2 is that the bootstrap capacitor C is practically directly connected to supply line +Vcc, which will cause pop-noise on terminal 6 at power-on. With the construction of FIG. 1A, several measures can be taken to cancel the pop-noise (for example, pulling down the base of transistor Q1 at power-on), but these measures are inoperative with the construction of FIG. 2.